The present invention relates to a method of fabricating a semiconductor device having a trench type element isolation structure.
In a semiconductor integrated circuit, it is required to control each element so as to be completely isolated from each other by eliminating electric interference between the elements. An isolation method with local oxidation (LOCOS) has been conventionally used as a method of electrically isolating elements. However, when the local oxidation is used, the isolation region develops a unique shape like a bird""s beak at its ends so as to expand the isolation region, which cause a problem of decreasing the active region of the elements. In a DRAM with an advanced microstructure, it is essential to have a shallow trench isolation (STI) structure where the elements are electrically isolated from each other by forming trenches in the substrate and burying insulators in the trenches so as to reduce the bird""s beak region developed at the ends of the isolation region.
FIGS. 9(a) and 9(b) are cross sectional views of the process steps showing the method of fabricating a conventional typical trench type element isolation structure. First, at the process step 1 an underlying silicon oxide film 2 and a silicon nitride film 3 are accumulated in this order onto a silicon substrate 1. At the process step 2 a mask (not shown) is formed onto the silicon nitride film 3, and then the silicon nitride film 3 and the underlying silicon oxide film 2 are patterned in this order so as to form a trench 13 in the silicon substrate 1. At the process step 3 a thermal oxide film 10 is formed on the inner wall of the trench by thermal oxidation, and at the process step 4 an oxide 11 is deposited onto the entire surface by a CVD method. At the process step 5 the oxide 11 formed on the silicon nitride film 3 is removed by a CMP method (Chemical Mechanical Polishing) using the silicon nitride film 3 as a stopper so as to leave the oxide 11 only inside the trench 13. At the process step 6 the silicon nitride film 3 is removed by a heat phosphate solution, and at the process step 7 the underlying oxide film 2 is removed by fluoric acid so as to complete a trench type element isolation structure. The first case of such a trench isolation method is disclosed in U.S. Pat. No. 4,104,086.
As shown in FIG. 10, as an improved trench isolation with the above-mentioned conventional structure, Japanese Unexamined Patent Publication No. 340950/1998 shows the case where a polycrystalline silicon film 4 is arranged between the underlying silicon oxide film 2 and the silicon nitride film 3. In this case, in the thermal oxidation shown at the process step 3xe2x80x2 the difference in oxidation rate between the silicon substrate 1 and the polycrystalline silicon film 4 makes it possible to expand the formation region of the thermal oxide film 12 towards the active region. This restricts the development of hollows when the element is completed (at process step 7).
In the method of fabricating a trench type element isolation structure, a level difference of xe2x88x92300 to 900 xc3x85 (hereinafter referred to as STI level difference) is caused between the oxide 11 for element isolation and the silicon substrate 1 as shown in FIGS. 11(a) and 11(b) due to variations in the thickness of the silicon nitride film 3, variations in the loss amount of the silicon nitride film 3 caused when the trench 13 is formed in the silicon substrate 1, variations in leveling process amount by the CMP method, and the like resulting from the process variations in the formation process. In the integrated circuit, as shown in FIG. 12, the electrode layer 23 deposited on the surface of the element is micro-etched to form a gate electrode on the isolation region Z1, so as to control the transistor formed in the active region Z2. When the STI level difference drops as shown in FIG. 11(b), the gate electrode is surrounded by the side wall of the active region, making the electric field be concentrated on the side wall so as to cause a decrease the threshold voltage of the transistor, which is referred to as reverse narrow channel effects. The reverse narrow channel effects increase as the semiconductor is integrated in larger densities and the widths of the active regions (intervals of the trenches) become narrower, making it very difficult to control the threshold voltage of the transistor. On the other hand, when the STI level difference becomes too large as shown in FIG. 11(a), it may cause inconveniences such as the development of etching residues in the level difference portions at the ends of the isolation region when the gate electrode is micro-etched. In order to avoid such inconveniences, it is preferable that the STI level difference is between 0 and 600 xc3x85.
The present invention has been contrived to solve the above-mentioned problems, with an object of providing a method of fabricating a trench type element isolation structure whose element suffers from little property deterioration by preventing a drop in the STI level difference of the trench type element isolation structure, and by controlling the height of the STI level difference at a proper level, so as to improve the yield and reliability of the element.
The first aspect of the present invention is a method of manufacturing a trench type semiconductor element isolation structure comprising steps of:
(i) forming a silicon oxide film on a silicon substrate and forming a silicon nitride film on the silicon oxide film;
(ii) forming a trench penetrating the silicon nitride film and the silicon oxide film, said trench reaching an interior of the silicon substrate;
(iii) forming a thermal silicon oxide film on an inner wall of said trench;
(iv) depositing a silicon oxide in said trench;
(v) subjecting said silicon oxide to a polishing treatment with the silicon nitride film used as a stopper layer leaving said silicon oxide only in the trench;
(vi) etching the silicon oxide by a predetermined amount according to at least one of the thickness of the silicon nitride film after the steps (i), (ii) and (v) and heights of the silicon oxide after the steps (iv) and (v);
(vii) etching the silicon nitride film after completing the step (vi); and
(viii) etching the silicon oxide film after completing the step (vii).
The silicon oxide is etched by in the step (vi) the predetermined amount according to a value based on a sum of a thickness of the silicon nitride film after the step (ii) and a height of the silicon oxide after the step (v) subtracted by a height of the silicon oxide after the step (iv).
The silicon oxide is etched in the step (vi) by the predetermined amount on the basis of a thickness of the silicon nitride film after the step (ii) and a second height of the silicon oxide after the step (v).
The second aspect of the present invention is a method of manufacturing a trench type semiconductor element isolation structure comprising steps of:
(i) forming a silicon oxide film on a silicon substrate and forming a silicon nitride film on the silicon oxide film;
(ii) forming a trench penetrating the silicon nitride film and the silicon oxide film, said trench reaching an interior of the silicon substrate;
(iii) forming a thermal silicon oxide film on an inner wall of said trench;
(iv) depositing a silicon oxide in said trench;
(v) subjecting said silicon oxide to a polishing treatment with the silicon nitride film used as a stopper layer leaving said silicon oxide only in the trench;
(vi) etching said silicon oxide by a predetermined amount after completing the step (v);
(vii) etching said silicon nitride film after completing the step (vi); and
(viii) etching said silicon oxide film and said silicon oxide based on an amount of dissolved silicon in an etchant in the step (vii).
The third aspect of the present invention is a method of manufacturing a trench type semiconductor element isolation structure comprising steps of:
(i) forming a silicon oxide film on a silicon substrate and forming a silicon nitride film on the silicon oxide film;
(ii) forming a trench penetrating the silicon nitride film and the silicon oxide film, said trench reaching an interior of the silicon substrate;
(iii) forming a thermal silicon oxide film on an inner wall of said trench;
(iv) depositing a silicon oxide in said trench;
(v) subjecting said silicon oxide to a polishing treatment with the silicon nitride film used as a stopper layer leaving said silicon oxide only in the trench;
(vi) etching said silicon nitride film after completing the step (v); and
(vii) etching said silicon oxide film and said silicon oxide by predetermined amount based on a measured value of a difference in surface level between said silicon oxide film and said silicon oxide.
The fourth aspect of the present invention is a method of manufacturing a trench type semiconductor element isolation structure comprising steps of:
(i) forming a silicon oxide film on a silicon substrate, forming a polycrystalline silicon film on said silicon oxide film, and forming a silicon nitride film on said polycrystalline film;
(ii) forming a trench by which said silicon nitride film, said polycrystalline silicon film and said silicon oxide film are penetrated, said trench reaching within said silicon substrate;
(iii) forming a thermal silicon oxide film on an inner wall of said trench;
(iv) depositing a silicon oxide in said trench;
(v) removing a part of said silicon oxide by a polishing process using silicon nitride film as a stopper layer leaving said silicon oxide only in said trench;
(vi) etching said silicon oxide by a predetermined amount after completing the step (v) based on at least one of measured values of a first thickness of said silicon nitride film formed in the step (i), a second thickness of said silicon nitride film after completing the step (ii), a first height of said silicon oxide deposited in said trench in the step (iv), a third thickness of said silicon nitride film after completing the step (v) and a second height of said silicon oxide after completing the step (v);
(vii) etching said silicon nitride film and said polycrystalline silicone film after completing the step (vi); and
(viii) etching said silicon oxide film after completing the step (vii).
The silicon oxide is etched by the predetermined amount on the basis of a value obtained by subtracting the first height of the silicon oxide from a sum of the second height of the silicon oxide and the second thickness of said silicon nitride film.
The silicon oxide is etched in the step (vi) by the predetermined amount on the basis of the second thickness of the silicon nitride film and the second height of the silicon oxide.
The fifth aspect of the present invention is a manufacturing a trench type semiconductor element isolation structure comprising steps of:
(i) forming a silicon oxide film on a silicon substrate, forming a polycrystalline silicon film on said silicon oxide film, and forming a silicon nitride film on said polycrystalline film;
(ii) forming a trench by which said silicon nitride film, said polycrystalline silicon film and said silicon oxide film are penetrated, said trench reaching within said silicon substrate;
(iii) forming a thermal silicon oxide film on an inner wall of said trench;
(iv) depositing a silicon oxide in said trench;
(v) removing a part of said silicon oxide by a polishing process using silicon nitride film as a stopper layer leaving said silicon oxide only in said trench;
(vi) etching said silicon oxide by a predetermined amount after completing the step (v);
(vii) etching said silicon nitride film, and then etching said polycrystalline film after completing the step (vi); and
(viii) etching said silicon oxide film and said silicon oxide by a predetermined amount based on amount of silicon dissolved in an etchant of said silicon nitride film in the step (vii).
The sixth aspect of the present invention is a method of manufacturing a trench type semiconductor element isolation structure comprising steps of:
(i) forming a silicon oxide film on a silicon substrate, forming a polycrystalline silicon film on said silicon oxide film, and forming a silicon nitride film on said polycrystalline film;
(ii) forming a trench by which said silicon nitride film, said polycrystalline silicon film and said silicon oxide film are penetrated, said trench reaching within said silicon substrate;
(iii) forming a thermal silicon oxide film on an inner wall of said trench;
(iv) depositing a silicon oxide in said trench;
(v) removing a part of said silicon oxide by a polishing process using silicon nitride film as a stopper layer leaving said silicon oxide only in said trench;
(vi) etching said silicon nitride film, and then etching said polycrystalline silicon film after completing the step (v);
(vii) etching said silicon oxide film and said silicon oxide by predetermined amount either a measured value of a difference in surface level between said polycrystalline silicon film and said silicon oxide which are formed by etching said silicon nitride film, or a measured value of a difference in surface level between said silicon oxide film and said silicon oxide which are formed by etching said polycrystalline silicon film.